The concept of hybrid wafer-scale integration systems, also abbreviated as WSI, already derives from the 1960's. The concept is based on the idea of integrating individual chips on a wafer that itself is inherently pluggable. Since the individual chips thereby contain LSI circuits it is thus possible to manufacture specific high-performance modules for various possible uses.
The significance of WSI circuits for various areas of employment has been increasing with the assistance of new design, manufacturing and test technologies and with the increasing need for LSI circuits and modules. 4-megabyte WSI memories thus already exist for commercial purposes, these having been manufactured in Japan by NTT Musashino Electrical Comm. Lab. in Tokyo and serving the purpose of storing the entire Kanji alphabet. In addition to such a storing possibility, WSI circuits also offer the possibility of formatting extremely complex, customized modules. The advantages of the wafer-scale integration systems lie, first, therein that a desired circuit is more highly integratable, that the connections of the chips to one another ensue via shorter leads and that, further, a lower number of terminals need be conducted out of the wafer. These advantages enhance the reliability of the desired circuit.
In discrete wafer-scale integration, pre-tested chips are mounted and bonded on a pre-wired wafer. Silicon usually serves as wafer substrate because the wafer wiring can be cost-beneficially produced with a standard multi-layer process. The conducting properties of such a wafer wiring, however, forbid the use of long leads at high clocks, so that intermediate drivers must be utilized. A further point of view when designing WSI systems is the heat elimination of the overall wafer-scale-integration system wherein up to 1000 watts can be converted into heat.
FIG. 1 shows a solution of the prior art directed to the problem of long leads given high timing clocks for WSI systems. Separate driver chips are shown here, these being connected between the individual chips. In addition, the separate driver chips must be placed relative to the actual function chips, must be bonded and tested. This is also known from the literature in the publication IEEE Spectrum, October 1984, "The Trails of Wafer-Scale Integration" by Jack F. MacDonald et al., page 35, right-hand column through page 36, left-hand column, whereby the said publication also provides an overview of the development and of the prior art with respect to wafer scale integration systems.
The disadvantages of additional driver chips are comprised in an increased wiring outlay, an increased surface requirement of the overall circuit as well as in additional testing for the separate driver chips.